1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an access time speed-up circuit for a semiconductor memory device.
2. Background of the Related Art
To shorten data access times, semiconductor memory devices have employed a page mode operation mode in which, when a predetermined address appears, all corresponding data are sensed and then held. When the next address appears, the data preliminary held are output. Thus in the page mode, the time required for address decoding and data sensing can be substantially reduced.
FIG. 1 shows the functional structure of a conventional semiconductor memory device that operates in the page mode. The conventional memory device of FIG. 1 has a normal address buffer 10 for receiving normal address signals AN.sub.1 .about.AN.sub.Y, and a page decoder 17 for converting 2.sup.n .times.m data bits read from a memory cell array 12 when using the normal address signals AN.sub.1 .about.AN.sub.Y to address m-bits of data during a decoding operation. The decoding operation addresses m data bits for each different 2.sup.n page address and is controlled by decoding signals generated from a page address buffer 16, which receives page address input signals AP1-APn.
FIG. 2 is a timing diagram showing data access timing according to the conventional semiconductor memory device of FIG. 1. t.sub.BA Denotes the time for buffering the normal address input signals AN.sub.1 -AN.sub.Y through the normal address buffer 10, for decoding the buffered normal address input signals through the X/Y decoder 11 and for sensing data from the memory cell array 12. After time t.sub.BA elapses, the data output operation with the page address input signals is accomplished in a time t.sub.PBA, such that each page of m-bit data sensed by the sense amplifier circuit 14 is converted to resultant output data. t.sub.PA denotes the time, referred to as one cycle time of page mode access operation, for generating all the data for each page of m-bit data.
The data access time, without use of page mode operation, for one page of data can be defined by an equation such as 2.sup.n .times.t.sub.BA (n denotes the number of page address bits). With use of page mode operation, this data access time becomes t.sub.BA +(2.sup.n -1). Assuming that time t.sub.BA is 150 nano-seconds for a conventional semiconductor memory device, time t.sub.PBA becomes 70 nano-seconds. Thus, when the value of n is 3, data access time (without page mode operation) is 1200 nano-seconds. With page mode operation, data access time is 640 nano-seconds. Clearly, page mode provides faster access times.
However, as shown in FIG. 2, the conventional page mode requires a time t.sub.BA for accessing the data of 2.sup.n .times.m bits whenever every page mode cycle is initiated.